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Conforms to POCSAG standard for pagers |
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512, 1200 or 2400 bps signal speed |
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Multiframe compatible (each address individually controllable) |
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8 addresses x 4 sub-address (total of 32 addresses) control |
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Built-in buffer memory |
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Supports tone, numeric or character call messages |
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Built-in input signal filter, with filter ON/OFF and 4 selectable filter characteristics |
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PLL-compatible battery saving method (BS1, BS2, BS3 outputs) |
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BS1 (RF control main output signal) 61-step setup time setting |
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BS2 (RF DC-level adjustment signal) before/during reception selectable adjustment timing |
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BS3 (PLL setup signal) 61-step setup time setting |
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1-bit and 2-bit burst error auto-correction function (messages) |
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25 to 75% duty factor signal coverage |
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8 rate error detection condition settings |
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76.8kHz system clock (crystal oscillator) |
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76.8 or 38.4kHz clock output pin |
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Built-in oscillator capacitor and feedback resistor |
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2.0 to 3.5V operating supply voltage |
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Molybdenum-gate CMOS process realizes low power dissipation |
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Package:SSOP-16-068044-1 |